In digital design, what is metastability in a flip-flop, and how do synchronizers mitigate it?

• A. Metastability occurs when a flip-flop output is unresolved due to input changes near the clock; synchronizers use multiple flip-flops to resolve it before reaching logic.
• B. Metastability occurs when the supply voltage fluctuates; synchronizers stabilize it with decoupling capacitors.
• C. Metastability is a desirable state that increases timing margins.
• D. Metastability causes permanent errors that cannot be mitigated by design.

Answer: (A)

Metastability happens when a flip-flop’s input changes very close to the clock edge, making the internal decision between 0 and 1 ambiguous. The flip-flop can enter a metastable state where its output doesn’t settle to a clean 0 or 1 right away, so downstream logic may see an unstable signal or miss a proper timing boundary.

Synchronizers address this by using multiple flip-flops in series, all clocked by the same clock. The first stage may still go metastable, but its output is fed into a second stage that provides additional time to resolve to a definite 0 or 1 before the signal propagates further. The chance that metastability propagates through all stages is very small, and adding stages or giving more settling time makes it even less likely.

This concept isn’t about supply voltage or decoupling, isn’t something to be desired, and isn’t permanent—designs can mitigate metastability with synchronizers to ensure reliable, stable data at the downstream logic.