What characterizes a flash ADC and why is it rarely used for high-resolution systems?

• A. It uses a single high-speed comparator to feed a reduced-resolution DAC.
• B. It uses an array of parallel comparators for instantaneous conversion; scalability is impractical for high resolution due to comparator count and power.
• C. It samples the input sequentially using a ramp reference.
• D. It converts by integrating the input signal and producing a digital output.

Answer: (B)

A flash ADC is built with an array of parallel comparators tied to a resistor ladder that provides the reference voltages. All comparisons happen at once, so the conversion is essentially instantaneous. The why behind the impracticality at high resolution is the hardware growth: to resolve N bits you need about 2^N minus one comparators, plus precise references and routing. As resolution rises, the number of comparators and the associated circuitry (ladder, interconnects, calibration) grows exponentially, consuming a lot of chip area and power and becoming difficult to fabricate with uniform accuracy. That’s why flash ADCs shine for very fast conversion at modest bit depths but become unwieldy for high-resolution needs.

The other descriptions don’t fit flash behavior: a single fast comparator feeding a reduced-resolution DAC describes a successive-approximation style, not parallel all-at-once comparison; sampling with a ramp reference suits ramp or integrating architectures; and integrating the input to produce digital output points to integrating (or dual-slope) ADCs.