What is a common method to mitigate metastability when routing asynchronous signals into a synchronous system?

• A. Use a synchronizer chain of two or more flip-flops in series to increase metastability resolution
• B. Increase clock frequency to outrun metastability
• C. Ignore metastability and rely on downstream logic
• D. Replace flip-flops with latches

Answer: (A)

When you sample an asynchronous signal with a clocked flip-flop, there’s a real possibility that the input changes close to the clock edge, sending the flip-flop into a metastable state where its output is uncertain for a short time. The way to handle this, reliably, is to give the signal additional time to settle before it drives the rest of the system. A chain of two or more flip-flops in series does exactly that: the first flip-flop captures the asynchronous event and may become metastable, but the second (and any subsequent) flip-flop samples the output on the next clock edge after the metastable state has likely resolved. Since the metastable state decays with time, adding stages reduces the chance that a metastable condition propagates to the final output; the final stage is far more likely to present a clean, stable value.

In practice, you typically use two stages because that gives a good balance of reliability and ease of design; more stages can be used for higher assurance in critical interfaces. It’s important to remember that metastability can’t be eliminated entirely, only mitigated through such synchronization delay.

Increasing the clock frequency doesn’t guarantee resolution and can even worsen the chance of metastability propagating, since the sampling occurs more often and doesn’t give the unstable state more time to settle. Ignoring metastability or relying on downstream logic is unsafe, and replacing flip-flops with latches would introduce other timing hazards due to their level-sensitive behavior.