What is metastability in digital circuits?

• A. Metastability is a stable 0 state
• B. Metastability is an indeterminate state between 0 and 1 caused by near-threshold input within setup/hold windows
• C. Metastability improves timing margins
• D. Metastability only occurs with asynchronous clocks

Answer: (B)

Metastability occurs when a digital latch or flip-flop has to decide between 0 and 1, but the input changes near the decision threshold inside the setup/hold window around a clock edge. In that moment the internal signaling is almost equally driven toward both states, so the output may not settle immediately and becomes indeterminate for a short period. It isn’t a valid 0 or 1 state, but a temporary condition that can take varying, unpredictable time to resolve to a definite value.

This happens most often when data changes close to a clock edge or when signals cross clock domains, and without enough time for the result to stabilize, it can affect downstream logic. Designers counter it by using synchronization stages (such as two flip-flops in series) so any metastable output has time to settle before feeding the next stage, and by ensuring proper setup and hold margins and avoiding asynchronous inputs directly driving synchronous elements.

So the described scenario—an indeterminate state between 0 and 1 caused by near-threshold input within setup/hold windows—is the best fit for what metastability is.