What is the impact of clock jitter on ADC performance, and how can it be mitigated?

• A. Jitter narrows the sampling window and improves SNR; mitigated by slower clocks.
• B. Jitter has no effect on ADC performance.
• C. Jitter broadens the sampling window but improves dynamic range; mitigated by increased sampling rate.
• D. Jitter broadens the sampling window, degrades SNR, and increases distortion; mitigated by clean clocks, PLLs with low jitter, and jitter-tolerant ADC designs.

Answer: (D)

Clock jitter injects timing uncertainty into the exact moment the ADC samples the input. When the input is changing, that small shift in sampling time translates into an amplitude error roughly equal to the slope of the signal times the timing error: ΔV ≈ (dV/dt) × Δt. That error behaves like additional noise and distortion, so the signal-to-noise and distortion ratio (SNDR) drops and harmonic distortion can rise. The impact grows with how fast the input is changing (higher frequency content or steeper slopes) and with how much jitter the clock has, making jitter a critical spec for high-speed or high-frequency ADCs.

Mitigation centers on reducing the sampling-time uncertainty and designing around it. Use a clean, low-jitter clock source and distribute it with a jitter-optimized clock tree or PLLs, plus good power supply decoupling and short, well-matched clock routes to minimize additional jitter and skew. Employ jitter-tolerant ADC architectures or techniques that mitigate aperture jitter, and consider synchronization strategies that keep the clock aligned with the input when possible. In short, the best protection against jitter-induced degradation is high-quality clocks and clock design, paired with ADCs built to tolerate some jitter.