What is the main advantage of edge-triggered flip-flops in synchronous circuits?

• A. They sample D only on the active clock edge, preventing changes during the sensitive window
• B. They continuously track input levels to reduce sampling error
• C. They invert the input to create a complement
• D. They generate the clock signal for the entire system

Answer: (A)

Edge-triggered flip-flops capture the input only at the moment of a clock transition. This means data is sampled precisely on the clock edge and does not follow changes to the input while the clock is high or low. The stability around that edge is ensured by setup and hold times, so the stored value is predictable and reliable for the next stage. This avoids glitches and timing hazards that would occur if the device tracked input levels continuously, as with level-sensitive latches. By latching on a single edge, these flip-flops support clean, synchronous data transfer and easier timing analysis, which is why capturing D only on the clock edge is the main advantage.