Which statement best describes the principle and timing operation of a successive-approximation-register (SAR) ADC?

• A. It performs a binary search by comparing the input with a DAC output; each clock edge determines the next bit until the code is resolved.
• B. It uses a bank of parallel comparators to achieve instant conversion.
• C. It integrates the input over time and outputs a value based on accumulation.
• D. It digitizes the input by sampling at an increasing sampling rate without feedback.

Answer: (A)

At the heart of a SAR ADC is a binary-search process guided by a DAC and a comparator. The input voltage is compared to the output of a DAC that is driven by a tentative code stored in a successive-approximation register. The conversion starts by guessing the most significant bit: set that bit high and keep the rest zero, then compare. If the input is larger than the DAC output, that bit stays 1; if not, that bit is cleared to 0. Move to the next bit and repeat, with each clock edge deciding one more bit. After as many clock cycles as there are bits, you have a full digital code that matches the input within the DAC’s resolution. This is different from a flash ADC, which uses many parallel comparators for instant conversion; or from integrating or delta-sigma types, which rely on time-based integration or oversampling with feedback. The SAR approach is efficient for mid-range speeds and power, delivering the result through a controlled, clock-driven sequence of decisions.