Which statement best differentiates a latch from a flip-flop in sequential logic?

• A. A latch is edge-triggered, while a flip-flop is level-sensitive.
• B. A latch is level-sensitive and transparent when its enable is active, while a flip-flop is edge-triggered and captures data on a clock transition.
• C. A latch requires an asynchronous reset, while a flip-flop never needs one.
• D. A latch cannot be used inside timing elements, while a flip-flop can.

Answer: (B)

The main idea is how these devices react to their control signals. A latch is level-sensitive and transparent when its enable is active: as long as the enable input is high, changes at the data input pass through to the output immediately. When the enable goes low, the last value that was present at the input is stored, so the output holds that value until the enable goes high again. This makes latches directly follow input during the enable interval and latch only when disabled.

A flip-flop, on the other hand, is edge-triggered. It samples and stores the input only on a clock transition (for example, the rising edge). Between clock edges, changes at the input do not affect the output, so the stored value remains stable until the next clock edge.

So the statement that best differentiates them is that a latch is level-sensitive and transparent when its enable is active, while a flip-flop is edge-triggered and captures data on a clock transition.

(Reasoning: the other ideas—latches being edge-triggered, latches requiring asynchronous resets, or latches being unusable in timing elements—don’t describe the fundamental timing difference to the same extent.)